As a conventional elevator electronic safety system (in particular, a method for checking a memory system), there has been proposed one which performs a check by the use of an error correction code (ECC) or the like, or a comparison check between two block memories (a main memory and an auxiliary memory)(see, for instance, Japanese patent application laid-open No. H08-16483).
According to such a conventional elevator electronic safety system, in checking a memory system, only an abnormality or malfunction check on memory data is carried out, but no check is performed at all as to whether a signal from a CPU is correctly input and output with respect to the address bus and the data bus that are used when memory is written and read. Accordingly, there has been a problem that the reliability of the malfunction check is low.
In particular, in case where very high reliability of the malfunction check is required as in the elevator electronic safety apparatus, low reliability of the malfunction check becomes a critical problem.
In addition, an additional circuit in this kind of system is almost composed of a built-in circuit, so it is required to form the additional circuit with a size as small as possible, thus making it difficult to take appropriate countermeasures.